Digital systems traditionally require a frequency source or "clock" as a reference for timing internal and external operations. The stability of the clock is not particularly demanding in those systems where all operations are timed by the same clock. However, in asynchronous transmission systems where all transfers are made from one synchronous system to another, even where the clock frequencies are the same on a long term basis, short term variations in either clock can degrade the data. Irrespective of clock stability at both ends of a transmission link, phase noise arises which is exaggerated at the receiver end because of external electrical disturbances or changing physical parameters in the transmission link or channel. These are called timing jitter. To this date, reduction of jitter at the receiver end, caused by the transmission channel has not been undertaken.
In the copending above referenced application, entitled Digital Data Recovery Using Delay Time Rulers, the applicant has disclosed a data recovery receiver system which does not employ a phase locked loop for data recovery but employs instead a system employing digitally controlled delay lines. The digitally controlled delay line time ruler data recovery system of our copending application is limited to use in situations where the peak-to-peak timing jitter is less than 50% of the nominal bit clock period. The invention of this patent is to provide apparatus and methods to reduce the timing jitter on serial-in digital data. A serial combination of this jitter correction apparatus and the aforementioned receiver will enable an increase in the useful range of the delay line time ruler type data separator for recovering data with peak-to-peak jitter greater than 50% in the presence of duty cycle distortion.
In a data transmission system, the receiver performs data recovery of the incoming serial signal data generated and sent by a transmitter and propagated through transmission medium. The edges of the transitions in the data stream provide both the data and the timing information of the transmitted data. These transitions are supposed to arrive at the receiver at time intervals that equal the bit period, or a multiple of the bit period. When no timing jitter is present in the data, these ideal timing instants are called timing "epochs." In practice, however, each edge arrives at an instant earlier or later than those epochs due to the timing jitter from various jitter sources. Jitter comes in both random and deterministic forms. Jitter that is completely random in nature is called Random Jitter (RJ). A partially random form of jitter is called Data Dependent Jitter (DDJ) which as its name implies, depends partially on the data sequence or data pattern. Deterministic jitter is typically the Duty Cycle Distortion (DCD) which mainly comes from unequal rising and falling delays arising from the channel, or various stages between the transmitting circuitry and the data recovery circuitry, which includes buffering, preamplification, level-translating and other coupling stages. The overall histogram of edge arrival times with respect to the timing epoch is the sum of the distribution of the various above sources of jitter. Depending on which jitter type is dominant, the total edge distribution could have only one peak, or could have multiple peaks. If the DCD jitter is dominant, two or more peaks will be observed. In other words, the peaks of the rising and falling edge distributions will not be coincident with the timing epoch.
The term "jitter correction" has been used in the prior art. However, in the prior art the jitter corrections were addressed to jitter introduced by different sources than the sources addressed by this invention. The prior art which addressed jitter compensation or reduction on the receiver side are mostly performed to remove or reduce the-effects of phase error or timing jitter introduced during the timing recovery process. One such example is U.S. Pat. No. 4,831,637 in which the timing jitter caused by the timing recovery circuit itself is reduced or eliminated. Another example is in U.S. Pat. No. 4,847,875 in which the timing jitter caused by the overhead bit or so-called stuffing bit removal is compensated.
A need exists to have a method and apparatus to reduce the timing jitter in serial incoming data or to reduce or to remove the Duty Cycle Distortion Components of the timing jitter.
A need also exists for an all-digital method and apparatus to correct a duty cycle distorted clock signal, when a 50% duty cycle signal is necessary. Prior art for achieving a perfect 50% duty cycle signal involves frequency multiplexing, that is to multiply the signal frequency to twice or higher, and then divide the frequency to its original value by using flip flops with matched clock-to-output-rise and clock-to-output-fall delays. Problems with these approaches relate to the higher frequency operations. Also, most often a phase locked loop (PLL) type analogue circuit is required to do the frequency multiplexing.